A ferroelectric memory (FeRAM: Ferroelectric Random Access Memory) including a ferroelectric capacitor is conventionally known as a nonvolatile memory capable of retaining its memory contents even when a power supply is turned off. Conventional ferroelectric memories are manufactured through, for example, the following manufacturing process.
FIG. 7A to FIG. 7H are schematic sectional views of a conventional ferroelectric-memory manufacturing method shown in process sequence in which a ferroelectric memory is produced.
In this manufacturing method, first, an N type impurity is injected into a surface part of a P type silicon substrate 201 as shown in FIG. 7A, and, as a result, an N+ type region 202 and N+ type region 203 are formed. Thereafter, thermal oxidation and patterning are performed, and, as a result, a gate insulating film 204 extending like a bridge from the N+ type region 202 to the N type region 203 is formed on the surface of the silicon substrate 201. Thereafter, polysilicon (doped polysilicon) densely doped with an impurity is deposited on the silicon substrate 201 by a CVD method, is then subjected to patterning, and, as a result, a gate electrode 205 is formed on the gate insulating film 204. Thereafter, by the CVD method, silicon oxide is deposited on the silicon substrate 201, is then subjected to etchback, and, as a result, a sidewall 206 surrounding a side wall of the gate electrode 205 is formed. In this way, a MOSFET 207 including the gate electrode 205 (Metal), the gate insulating film 204 (Oxide), the silicon substrate 201 (Semiconductor) having the N+ type region 202 (Drain region) and the N+ type region 203 (Source region) is formed as shown in FIG. 7A.
After forming the MOSFET 207, a first insulating layer 208 made of silicon oxide is stacked on the silicon substrate 201 by the CVD method. Thereafter, the first insulating layer 208 is subjected to patterning. As a result, a drain contact hole 209 leading from the upper surface of the first insulating layer 208 to the N+ type region 202 (Drain region) is formed. Additionally, a source contact hole 210 leading from the upper surface of the first insulating layer 208 to the N+ type region 203 (Source region) is formed.
Thereafter, by the sputtering method, a conductive material that contains titanium is deposited such that the inner surface of the drain contact hole 209 and the inner surface of the source contact hole 210 are covered with the conductive material and such that the upper surface of the first insulating layer 208 is covered therewith. Thereafter, by the CVD method, tungsten is deposited such that the drain contact hole 209 and the source contact hole 210 are filled with this tungsten. Thereafter, the conductive material that contains titanium and the tungsten material are polished by CMP treatment until the upper surface of the tungsten material and the upper surface of the first insulating layer 208 become flush with each other. In this way, a drain contact plug 213 embedded in the drain contact hole 209 is formed via a barrier film 211 as shown in FIG. 7A. Additionally, a source contact plug 214 embedded in the source contact hole 210 is formed via a barrier film 212. The drain contact plug 213 is brought into electric contact with the N+ type region 202 (Drain region) via the barrier film 211. On the other hand, the source contact plug 214 is brought into electric contact with the N+ type region 203 (Source region) via the barrier film 212.
Thereafter, by the sputtering method, a lower conductive material film 215 made of a conductive material that contains Ir (iridium), a ferroelectric material film 216 made of PZT (titanic acid lead zirconate), and an upper conductive material film 217 made of a conductive material that contains Ir (iridium) are stacked in this order on the first insulating layer 208 as shown in FIG. 7B. As a result, a layered structure 239 is formed on the first insulating layer 208.
Thereafter, as shown in FIG. 7C, a hard mask 240 made of TiN is formed at a part of the layered structure 239 located on the drain contact plug 213. Thereafter, the layered structure 239 is etched via this hard mask 240 at an etching temperature of 300° C. or more. In this way, a ferroelectric capacitor 221 consisting of the lower electrode 218, the ferroelectric film 219, and the upper electrode 220 is formed on the drain contact plug 213. The lower electrode 218 of the ferroelectric capacitor 221 comes into contact with the drain contact plug 213, and, as a result, is electrically connected to the N+ type region 202 (Drain region) via the drain contact plug 213. The hard mask 240 that has been thinned by etching remains on the upper electrode 220.
Thereafter, alumina is deposited on the first insulating layer 208 by the sputtering method, and, in addition, SiN is deposited thereon by the PECVD method. As a result, as shown in FIG. 7D, a first hydrogen barrier film 222 and a second hydrogen barrier film 223 are formed to protect the ferroelectric capacitor 221 from hydrogen.
Thereafter, by the CVD method, a second insulating layer 224 made of silicon oxide is stacked on the second hydrogen barrier film 223 as shown in FIG. 7E.
Thereafter, the second insulating layer 224 is polished by CMP treatment, and the upper surface of the second insulating layer 224 is flattened. Thereafter, as shown in FIG. 7F, the second insulating layer 224, the second hydrogen barrier film 223, and the first hydrogen barrier film 222 are subjected to patterning. As a result, a PL wiring via-hole 225 leading from the upper surface of the second insulating layer 224 to the hard mask 240 is formed. Additionally, a BL wiring via-hole 226 leading from the upper surface of the second insulating layer 224 to the source contact plug 214 is formed.
Thereafter, by the sputtering method, a conductive material that contains titanium is deposited such that the inner surface of the PL wiring via-hole 225 and the inner surface of the BL wiring via-hole 226 are covered therewith and such that the upper surface of the second insulating layer 224 is covered therewith. Thereafter, by the CVD method, tungsten is deposited such that the PL wiring via-hole 225 and the BL wiring via-hole 226 are filled therewith. Thereafter, the conductive material that contains titanium and the tungsten material are polished by CMP treatment until the upper surface of the tungsten material and the upper surface of the second insulating layer 224 become flush with each other. In this way, as shown in FIG. 7G, a PL wiring plug 229 embedded in the PL wiring via-hole 225 is formed via the barrier film 227. Additionally, a BL wiring plug 230 embedded in the BL wiring via-hole 226 is formed via the barrier film 228. The PL wiring plug 229 is brought into electric contact with the upper electrode 220 via the barrier film 227 and the hard mask 240. On the other hand, the BL wiring plug 230 is brought into electric contact with the source contact plug 214 via the barrier film 228.
Thereafter, by the sputtering method, a conductive material that contains titanium, a conductive material that contains aluminum, and a conductive material that contains titanium are stacked on the second insulating layer 224, and are subjected to patterning. As a result, a PL wiring 231 (i.e., a wiring that has a three-layer structure consisting of a titanium layer 233, an aluminum layer 234, and a titanium layer 235) that is brought into electric contact with the PL wiring plug 229 and a BL wiring 232 (i.e., a wiring that has a three-layer structure consisting of a titanium layer 236, an aluminum layer 237, and a titanium layer 238) that is brought into electric contact with the BL wiring plug 230 are formed as shown in FIG. 7H.
Thereafter, a word line 241 is connected to the gate electrode 205, and a plate line 242 is connected to the PL wiring 231, and a bit line 243 is connected to the BL wiring 232.
In this way, the ferroelectric memory 200 including the ferroelectric capacitor 221 can be obtained as shown in FIG. 7H.